Safehubcollective.org

Save your time and search cool lifehacks here!

## What is Casex and casez statement?

The case, casex and casez all do bit-wise comparisons between the selecting case expression and individual case item statements. casex ignores any bit position containing an X or Z; casez only ignores bit positions with a Z. Verilog literals use the both the ? and z characters to represent the Z state.

What are synthesizable and non-synthesizable constructs?

Synthesizable Verilog is that subset of the language that are accepted by the synthesis tools. The non-synthesizable constructs are used only for simulation and the synthesis tool cannot handle them.

### Which values are considered as Don T Cares in casez statement?

Casez statement treats z as dont care. It mean what it sounds, ‘don’t care’ (dont care whether the bit is 0,1 or even x i.e, match z(?) to 0 or 1 or x or z).

What is Synopsys parallel case?

A “parallel” case statement is a case statement in which it is only possible to match a case expression to one and only one case item. Parallel / no (Figure 9) – The case statement was not recognized to be “parallel” by Synopsys.

#### What is casez?

Casez allows one to mark certain bits (using Z or ?) in both the case item and case expression as wildcard in the comparison. If a bit is marked as a wildcard, then it becomes a don’t care and will match any value (0, 1, Z, X).

What is meant by synthesizable?

Filters. (chemistry) Able to be (easily) synthesized. adjective.

## What is the difference between wire and reg?

wire elements must be continuously driven by something, and cannot store a value. Henceforth, they are assigned values using continuous assignment statements. reg can be used to create registers in procedural blocks. Thus, it can store some value.

How parallel case and full cases problems are avoided in SV?

2) How parallel case and full cases problems are avoided in SV? something different about the design than what is told to the simulator. perform certain optimizations that are unknown to the simulator. can be matched to a case item or to a case default.

### How do you define timescale in Verilog?

Verilog simulation depends on how time is defined because the simulator needs to know what a #1 means in terms of time. The `timescale compiler directive specifies the time unit and precision for the modules that follow it.

Can a task called a function?

A task must be specifically called with a statement. It cannot be used within an expression as a function can.